Analog/Mixed-Signal-AMS Design Verification Engineer

Summary

Join our team as an Analog/Mixed-Signal Design Verification Engineer. You will be responsible for extracting modeling specifications, developing SystemVerilog models and UVM testbenches, running simulations, and collaborating with designers and layout engineers. This role offers the opportunity to directly influence design changes and troubleshoot issues. You will also support model integration and contribute to timing model development. Success in this position requires a strong understanding of SystemVerilog, digital design, and mixed-signal concepts.

Requirements

• Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc
• Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g band-gap, PLL, Amplifier, Filters)
• Familiarity with behavioral Verilog code for an analog circuit
• Ability to write thorough test benches for digital and AMS simulators
• Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating
• Familiarity with timing closure and static timing analysis tools
• Experience with scan chain vector generation and verification

Responsibilities

• Extract modeling specifications from designers
• Develop Analog/Mixed-Signal model in System-Verilog
• Develop UVM Testbench and developing test cases
• Run simulation and fix the behavioral model working with Circuit designer
• Develop timing model for the circuit working with layout engineer
• Determine whether anomalous symptoms are caused by errors in the specifications, models, testbench, or design
• Support integration of composite models into larger composite models maintained by other groups