FPGA Digital Design Engineering Intern

Summary

Join Kepler Communications, a company revolutionizing space internet connectivity, as an FPGA Digital Designer Engineering Intern. Contribute to the development of next-generation satellites and earth stations by writing RTL code. This internship offers opportunities to work with software-defined radio and networks, design custom IP, and support new communication interfaces. The position is available for a full-time term (4, 8, 12, or 16 months) starting September 2025, with flexible work arrangements (onsite, hybrid, or remote). Kepler is committed to fostering an inclusive and accessible work environment.

Requirements

• 2+ years in an Electrical or Computer Engineering degree program, or equivalent
• Experience with Verilog, SystemVerilog, or VHDL. (You will be working in SystemVerilog)
• Currently enrolled in an undergraduate program at a Canadian post-secondary institution
• Available for a full-time, 4, 8, 12 or 16 month internship beginning September 2025
• Opportunity to work out of our new Toronto office! This position can be based onsite at our Toronto office (24 Ward Street), hybrid, or remote, depending on the candidate’s location

Responsibilities

• Maintain and add new functionality to our FPGA code base, including code to control and test our SDR (software-defined radio) and SDN (software-defined network)
• Design custom IP for new features of both Kepler's satellites and ground stations
• Add support for new sensors/communication interfaces (such as SPI, I2C, UART)
• Work with high-speed FPGA interfaces (e.g. JESD204b, 10G Ethernet, Aurora)

Preferred Qualifications

• Experience with DSP (digital signal processing) algorithms
• Strong skills with C++ and embedded programming
• Strong scripting experience (e.g. bash, Python, Tcl, etc.)
• Relevant experience through hobbies or a university design team