Enfabrica is hiring a
Hardware Emulation Engineer

Summary

The job is for an Emulation Engineer at Enfabrica, a startup revolutionizing AI compute systems. The role involves building a new product, maintaining emulation infrastructure, and working cross-functionally. Remote work is possible.

Requirements

• Emulation experience on any of the emulation platforms : Palladium, Zebu or Veloce
• Experience with emulation compile flow, wave dump & triggers, waveform debug, running tests
• Experience writing scripts in Perl or Python
• Exposure to Makefile, Bazel or other build flows
• Experience with waveform debug tools such as Verdi/SimVision/Indago
• Good understanding of Verilog and SystemVerilog RTL design
• Exposure to synthesizable SystemVerilog/Verilog code and SVAs
• Strong communication skills and a team player
• MS with 5+ years of experience, BS with 7+ years experience

Responsibilities

• Collective ownership of emulation build infrastructure
• Collective ownership of chip level emulation models
• Development and ownership of Github based CI/CD flows for emulation code base
• Own and maintain emulation infrastructure
• Own and maintain chip level emulation models for validating different subsystems within a networking chip
• Work with vendors on hardware and tool issues on a need basis
• Enhance emulation methodology for robustness, test throughput, portability and debuggability
• Work cross functional with simulation, firmware and software test team to validate the chip pre-silicon. Support SW test bring up and debug on hardware emulator, collaborate with hardware design team to triage and fix design issues
• Leverage understanding of simulation based design verification flows to help emulation test-planning and execution
• Work cross functional with simulation, firmware and software test team to repro failures seen in real silicon on the emulator

Preferred Qualifications

• Working knowledge of PCIE, Ethernet, AXI, DDR, etc
• Working knowledge of UART, SPI, JTAG, QSPI, etc
• Working knowledge of ARM based processors
• Exposure to Design Verification and System Verilog, UVM, and C/C++ verification environments. Be able to correlate stimulus between simulation and emulation