Remote Hardware Emulation Engineer

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Enfabrica

πŸ’΅ $120k-$160k
πŸ“Remote - United States

Job highlights

Summary

Join an ambitious team of silicon and distributed systems experts as a hardware emulation engineer. You will build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and help solve key infrastructure challenges facing our customers.

Requirements

  • Emulation experience on any of the emulation platforms : Palladium, Zebu or Veloce
  • Experience with emulation compile flow, wave dump & triggers, waveform debug, running tests
  • Experience writing scripts in Perl or Python
  • Exposure to Makefile, Bazel or other build flows
  • Experience with waveform debug tools such as Verdi/SimVision/Indago
  • Good understanding of Verilog and SystemVerilog RTL design
  • Exposure to synthesizable SystemVerilog/Verilog code and SVAs
  • Strong communication skills and a team player
  • MS with 5+ years of experience, BS with 7+ years experience

Responsibilities

  • Own and maintain emulation infrastructure
  • Own and maintain chip level emulation models for validating different subsystems within a networking chip
  • Work with vendors on hardware and tool issues on a need basis
  • Enhance emulation methodology for robustness, test throughput, portability and debuggability
  • Work cross functional with simulation, firmware and software test team to validate the chip pre-silicon. Support SW test bring up and debug on hardware emulator, collaborate with hardware design team to triage and fix design issues
  • Leverage understanding of simulation based design verification flows to help emulation test-planning and execution
  • Work cross functional with simulation, firmware and software test team to repro failures seen in real silicon on the emulator

Preferred Qualifications

  • Working knowledge of PCIE, Ethernet, AXI, DDR, etc
  • Working knowledge of UART, SPI, JTAG, QSPI, etc
  • Working knowledge of ARM based processors
  • Exposure to Design Verification and System Verilog, UVM, and C/C++ verification environments. Be able to correlate stimulus between simulation and emulation

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