Remote HW Verification Engineer

Summary

Join the Eclipse Foundation Europe GmbH as a Hardware Verification Engineer for the OpenHW Europe Working Group to verify at industrial-grade open-source IPs based on RISC-V. The role primarily contributes to the TRISTAN project and other upcoming research projects.

Requirements

• Be very confident with SystemVerilog and UVM for use with coverage-driven, constrained-random verification strategies
• A working knowledge of: Linux, Make, and Python
• Computer architectures of general-purpose CPUs
• Peripheral busses, interrupt controllers, and peripherals such as UART, SPI, and GPIOs
• A commercial SystemVerilog simulator and associated debug and coverage tools

Responsibilities

• Use SystemVerilog and UVM to create and extend our testbenches: you should know how to verify IPs with random instructions
• Verify CPUs based on RISC-V
• Verify peripherals such as UART, SPI, GPIOs, interrupt controllers, and interconnects
• Integrate and extend existing CPUs to support extra features
• Integrate and extend new co-processors
• Carry out typical development tasks including dissemination, reporting, etc
• Support the specific initiatives of the OpenHW Technical Working Group to drive interest, participation, and adoption beyond just the TRISTAN project
• Support the broader objectives of the Eclipse Foundation’s European research team, including leading activities, initiating and organizing dissemination and community-building activities, facilitating project participation at events, enabling dissemination through web assets, newsletters and Eclipse-related social media, completing regular reporting as required by the EU processes, supporting research project developers in working with the Eclipse Development Process (EDP) and open source and open hardware best practices, representing the Eclipse Foundation and OpenHW Europe working group at research project meetings and reviews, encouraging synergies among the EU projects and Eclipse Foundation members

Preferred Qualifications

Familiarity with Formal Verification, RTL design, RISC-V ISA, and Git would also be an asset