Senior NAND Logic Design/Verification Engineer

Summary

Join Solidigm as a logic design and/or verification engineer to play a central role in ensuring performance of 3D NAND designs.

Requirements

• A Master's degree in Electrical or Computer Engineering with at least 5 years of relevant NAND experience, or a bachelor's degree in Electrical or Computer Engineering with 7+ years of relevant experience
• Proficiency in Verilog, System verilog and industry standard logic simulation tools is a must
• Expertise in test bench development using system verilog and UVM/OVM concepts. Experience in test generation, SVA, coverage analysis, failure debugging is a must
• Automating using Perl, Python,C/C++ or TCL is a plus

Responsibilities

• Design logic and develop microcode to enable features to improve performance
• Perform logic verifications of 3D NAND designs using latest methodologies
• Generate verification and coverage plans, construct necessary ULT test benches and fullchip models to achieve comprehensive coverage
• Troubleshoot and resolve logic and microcode bugs within pre-si verification and post Si validation
• Collaborate with architects, analog and Core designers and APR teams to enhance and achieve power, performance and functional targets
• Formulate functional and Dfx test plans that are comprehensive including system centric validation tests

Benefits

$127,260 - $203,620 compensation range for this role