Silicon Logic Formal Verification Engineer

Summary

Join our team as a Formal Verification Engineer and contribute to the formal verification of CPU, Fabric, and Accelerator design. As a key member of our team, you will work with architects and RTL design engineers to identify, specify, and verify artifacts amenable to formal analysis. You will prove functional and security properties of the design, find design bugs, and develop sound formal abstract models for verifying system-level properties.

Requirements

• Solid understanding of formally specifying and analyzing temporal assertion properties
• Hands-on experience using model checking tools
• Experience with interactive theorem provers is a plus
• Excellent problem-solving skills, along with strong written and verbal communication abilities
• Excellent organizational skills and high self-motivation
• Ability to communicate and work well with different design teams
• PhD, Master’s Degree, or Bachelor’s Degree in a technical subject area

Responsibilities

• Work with architects and RTL design engineers to identify, specify, and verify artifacts amenable to formal analysis
• Prove functional and security properties of the design, find design bugs, and work closely with design teams to deliver high-quality designs
• Develop sound formal abstract models for verifying system-level properties like deadlock freedom and non-starvation using formal methods
• Develop innovative flows using formal methods in conjunction with simulation-based techniques for effective bug hunting
• Develop reusable and scalable proof techniques