Rivos Inc. is hiring a
Silicon Packaging Substrate Design Engineer

Summary

The Packaging Substrate Designer is responsible for silicon packaging substrate pathfinding, competitive analysis, mockup design, ball map assignment, package outline drawing (POD), signal and power routing, optimization, design release, and post-assembly analysis. The role involves working with cross-functional teams to select the optimized package solution, designing custom substrates and interposers, optimizing die floorplan, bump patterns, and stackup, owning deliverables at critical design checkpoints, and working with overseas assembly partners for product bring-up, qualification, and ramp to HVM.

Requirements

• Experience in substrate layouts and design in advanced package technologies
• Experience or knowledge of 2.5D , and 3D package substrate and interposer design
• Experience with design teams on floor plan, bump, and layout optimization
• Strong authority on Cadence Allegro Package Designer (APD)
• Excellent problem-solving, written and verbal communication skills, and organization skills
• Self-motivated
• Ability to work well in a team and be productive under aggressive schedules
• PhD, Master's, or BS Degree with 7+ years of experience in the subject area

Responsibilities

• Silicon packaging substrate pathfinding
• Competitive analysis
• Mockup design
• Ball map assignment
• Package outline drawing (POD)
• Signal and power routing
• Optimization to meet SIPI, thermal, and mechanical requirements
• Design release
• Post-assembly analysis