MIPS is hiring a
Sr. CPU Verification Engineer

Summary

The job is for a CPU Verification Engineer at MIPS, requiring 7+ years of industry experience in functional verification of CPUs, familiarity with ASIC design verification tools, Interconnect protocols like AXI/ACE/OCP/CHI, scripting in Python/Perl/TCL/Shell, and strong knowledge of Verilog/SystemVerilog/C/C++/Assembly. Preferred qualifications include experience with Multicore Processors, System Verilog assertions, UVM, RISC-V, ARM, MIPS CPU, functional safety flows, and assembly level programming.

Requirements

• Bachelors/Masters in Electronics/Electrical/Computer Engineering
• 7+ years of industry experience with a focus on functional verification in CPU verification
• Familiarity with CPU architectures and superscalar designs and industry leading RISC processors
• Exposure to various ASIC design verification tools with good digital design concepts
• Knowledge and experience with Interconnect protocols like AXI/ACE/OCP/CHI
• Scripting experience in Python/Perl/TCL/Shell
• Experience in creating functional test plans and implementing them as part of pre-silicon verification
• Strong knowledge of Verilog/SystemVerilog/C/C++/Assembly
• Strong analytical and problem-solving skills
• Self-motivated with excellent communication and presentation skills, and ability to collaborate well locally and with global team

Responsibilities

• Extensive hands-on experience with CPU verification using industry standard functional verification methodologies, formal verification and constrained random generators and reference model-based checkers
• Take critical decisions and completely own verification closure for a block or feature
• Cross functional interaction with CPU designers and architects and working across sites to ensure high quality CPU designs for customers

Preferred Qualifications

• Experience working with Multicore Processors or other complex pipelined digital products
• Experience in writing System Verilog assertions
• Experience with UVM
• Understanding of Assembly level programming
• Experience with RISC-V, ARM, and/or MIPS CPU
• Experience with multi core and coherency in modern systems
• Familiarity with functional safety flows and requirements

Benefits

Medical, dental, vision, retirement savings, and paid leave benefits