Remote Senior ASIC EDA Workflow Engineer

Summary

Join a fast-paced startup company as a senior ASIC engineer to lead EDA tools and engineering workflow development for multimodal generative AI inference acceleration products.

Requirements

• 10+ years of hands-on ASIC engineering experience
• Deep knowledge of VLSI/SoC chip design and verification workflows, with ASIC EDA tool suites from Synopsys and/or Cadence
• Strong programming and debugging skills with SystemVerilog as well as with key languages to automate tasks and improve efficiency like C/C++, Perl, TCL, and Python
• Experience leading the development and support for compilation, build automation, testing, packaging, and installation project generators
• Prior work experience with onboarding and supporting ASIC engineers with EDA workflows
• Expert level knowledge of Linux system administration and familiarity with cloud-based devops (IaC, CaC, etc.)
• Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field

Responsibilities

• Lead EDA tools and associated engineering workflow development for Recogni’s multimodal generative AI inference acceleration products
• Guide and assist colleagues to improve and invent EDA workflows within a fast-paced, agile HPC development environment
• Drive Recogni’s optimization, implementation, and exploration of new EDA tools and technologies for the full ASIC chip design process