Aeva is hiring a
Senior SoC Verification Engineer

Summary

The job is for a Senior SOC Verification Engineer who will lead a team to verify advanced ARM-based SoCs using 4-D Lidar. The role involves architecting and developing verification environments, defining and executing test plans, working with cross-functional teams, and achieving 100% coverage closure.

Requirements

• 8+ years of experience in design, verification, and validation of advanced ARM based SOCs
• 5+ years in architecting and building constrained random verification environments, reference models, scoreboards, and directed self-checking tests using SystemVerilog and UVM methodologies
• Deep understanding of ARM-based SOC verification. Writing assembly and C/C++ diagnostic firmware for embedded ARM processors and debugging in a simulation environment
• Working experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes, etc
• Solid programming skills in SystemVerilog, UVM, C/C++, assembly, Perl/Python
• Proficient in debugging complex SOC or CPU core designs
• Excellent verbal and written communication skills
• Ability to collaborate deeply with cross-functional leads and management teams
• Ability to deliver results in a very fast-moving environment

Responsibilities

• Lead and drive block, subsystems, and full-chip verification of advanced ARM-based SOCs
• Architect and build test benches, reference models, and scoreboards using SystemVerilog and UVM-constrained random methodologies
• Define and execute test plan for block, subsystem, and full-chip using SV/UVM and C/C++ FW running on the on-chip ARM processors
• Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define and enhance the processes, methodology, and tools to verify complex SoCs
• Work with Architects, design and verification, and system software teams to define system-level verification plans and prove that SOC meets the functional, performance, and power target defined in the architecture and design specs
• Identify and write functional coverage groups to improve test/stimulus quality

Preferred Qualifications

• Diagnostics Firmware development and validation
• Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu
• Post-silicon bring-up and validation planning and execution