Remote Senior Staff Design Verification Engineer

Summary

Join Untether AI as a Senior Staff Design Verification (DV) Engineer to verify new blocks and sub-systems, ensuring they meet all functional and performance requirements. As part of this talented team, you will collaborate with bright engineers tackling tough problems at the intersection of AI and hardware.

Requirements

• BSc/MS/PhD in EE/CE/CS, or equivalent
• Prior 8+ years of experience in RTL Design Verification (Verilog/SystemVerilog)
• Working experience in design/RTL Verification with SV/UVM
• Experience with Object Oriented Programming concepts
• Experience with various verification tasks - test plan development, test bench development, simulation/waveform debug, coverage analysis
• Good verbal and written communication skills
• Ability to work independently and as part of a team
• Problem-solving and troubleshooting skills; ability to take initiative and solve problems

Responsibilities

• Develop verification plans based on design specifications, architectural documentation, and technical requirements
• Design, implement, and maintain verification environments, including testbenches, simulation models, and test scripts
• Create and execute test cases to validate the functionality, performance, and robustness of hardware designs
• Work closely with design engineers and project managers to achieve verification goals and meet project timelines

Preferred Qualifications

• Working experience with the following protocols is a plus: PCI Express Gen4-6, HBM, UCIE, AMBA (APB, AHB, AXI, CHI, CSX)
• Good understanding of computer architecture
• Knowledge of memory interfaces (DDR/LPDDR/etc.)
• Working knowledge of Linux
• Working knowledge of C/C++/Assembly is a plus
• Working knowledge of Python/Perl
• Knowledge of Deep Learning concepts and frameworks is a plus
• Experience in managing a team of 2 to 5 DV engineers is a plus

Benefits

• 20 vacation days
• Strong health and extended health benefits
• Unlimited sick days
• Stock options