Senior Digital Verification Engineer

Summary

Join PsiQuantum's Electronic Sub-Systems team as a Senior Digital Verification Engineer to contribute to the development of innovative digital microarchitecture for FPGAs and ASICs. You will be responsible for the development and ownership of design verification test benches, including checkers, monitors, scoreboards, assertions, and functional coverage. The role involves developing test plans and cases to cover design features, working closely with design teams on debugging, and creating documentation and reports. This position requires a degree in a related field, 10+ years of industrial experience, and expertise in SystemVerilog, UVM, and constrained-random verification environments. Experience with silicon bring-up, FPGAs, and scripting languages is also essential. The ideal candidate will possess excellent communication and collaboration skills.

Requirements

• Degree in computer engineering, electrical engineers, computer science, or related field. MS preferred
• 10+ years industrial experience in related fields
• Experience with SystemVerilog
• Experience in verification and general design and verification concepts
• Experience in developing Monitors, Scoreboards and Sequencers that utilize SystemVerilog and UVM
• Ability to create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM)
• Experience in Silicon bringup
• FPGA experience
• Experience in scripting languages such as Python

Responsibilities

• Development and ownership of DV (design verification) test bench, including checkers, monitors, scoreboards, assertions and functional coverage
• Develop test plan and test cases to cover design feature set. This involves planning the verification of complex digital design blocks, understanding the design specification, and interacting with design engineers to identify important verification scenarios
• Work closely with design teams on failure debug, code coverage and functional coverage closure
• Debug regression failures and identify bug fixes
• Creating documentation and reports

Preferred Qualifications

• Understanding standard bus protocols like AXI, SPI, I2C would be a plus
• Ability to collaborate effectively across departments, sites, and time zones and adapt to dynamic environment
• Excellent communication skills

Benefits

• U.S. Base Pay Range$161,000 — $190,000 USD
• Bay Area Pay Range$185,000 — $200,000 USD