SOC Verification Engineer

Summary

Join an ambitious team of silicon and distributed systems experts as a design verification engineer. Build a groundbreaking new product that revolutionizes the performance and scalability of next-generation distributed computing systems and help solve key infrastructure challenges. The ideal candidate has experience building comprehensive verification frameworks and executing simulation test plans for large-scale networking and computing chips. This is a fast-paced, dynamic startup environment. The default location is Mountain View, CA, but remote candidates are welcome.

Requirements

• Experience with large SOC verification
• Familiar with SystemVerilog/UVM
• Minimum 3 years of experience in the ASIC verification field

Responsibilities

• Work in the SOC DV team to perform end to end verification of a large SOC
• Define and review a comprehensive SOC verification plan, including the test strategy, specific test cases, and coverage metrics
• Cover various aspects of SOC verification, including functional testing, integration verification, performance verification etc

Preferred Qualifications

• Experience with block to SOC verification reuse methodology is a plus
• Experience with firmware based verification is a plus
• Experience with large scale SOC TB performance optimization is a plus
• Experience with high speed interface protocol like PCIE/CXL/DDR/Ethernet is a plus
• Experience with ARM SOC bring up is a plus