📍United States
Director, Digital Design Verification
Fabric Cryptography
📍Remote - United States
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Summary
Join Fabric, a fast-growing Series A company, as their Director of Design Verification! Lead and manage the design verification team, ensuring high-quality silicon for our innovative VPU. You will develop and implement advanced test-bench environments and collaborate with cross-functional teams. Leverage your expertise in SystemVerilog, UVM, and random constrained testing to verify complex designs. This role requires 15-20+ years of design verification experience and strong leadership skills. Fabric offers competitive salaries, comprehensive benefits, flexible vacation, and remote work options.
Requirements
- Bachelor’s degree in electrical engineering or related fields; advanced degrees (MS, PhD) are a plus
- 15-20+ years of design verification experience, with a strong background in building testbench environments and developing design verification processes. 5-10 years of experience managing/leading/building teams
- Excellent verbal and written communication skills, with the ability to clearly communicate complex concepts to stakeholders
- Extensive experience in building block, CPU, and SOC testbench development
- Proficient in SystemVerilog and UVM
- Strong understanding of randomly constrained testing methodologies
- Experience with formal verification flow and tools
- Proficiency in Python
- In-depth knowledge of ASIC design flow
- Experience with silicon bring-up, debug, and manufacturing ATE support
- Proven track record of delivering high-quality, bug-free silicon
Responsibilities
- Lead and manage the design verification team to ensure the delivery of high-quality, bug-free silicon
- Develop and implement advanced test-bench environments and design verification processes
- Collaborate with cross-functional teams, including design, architecture, and software, to ensure comprehensive verification coverage
- Develop and execute verification plans, including block-level and system-on-chip (SOC) level testbenches
- Utilize SystemVerilog and UVM for the development of sophisticated verification environments
- Apply randomly constrained testing methodologies to thoroughly verify complex designs
- Employ formal verification flow and tools to ensure design correctness
- Develop and maintain Python and/or Perl scripts to support verification activities
- Ensure thorough documentation and clear communication of verification concepts and results to stakeholders
Preferred Qualifications
Familiarity with emulators, development boards and systems, or system simulators and software integrated verification efforts is a plus
Benefits
- Competitive salary and benefits
- Comprehensive medical / dental / vision, STD/LTD, AD+D and Life Insurance
- Flexible vacation and company paid holidays
- We’re remote friendly
- We believe that your value to the team can be provided at one of our offices or from the comfort of your home. Depending on your function, enjoy the flexibility of remote work and join our growing community of remote employees in the US and around the world
- You won’t just own your work here; you’ll have the potential to own equity in our company
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