Senior Design Verification Engineer

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MIPS

๐Ÿ’ต $165k-$195k
๐Ÿ“United States

Job highlights

Summary

The job description is for a Senior Verification Engineer position at MIPS. The role involves hands-on experience in CPU verification using industry-standard methodologies, working with designers and architects, developing test plans, analyzing coverage, and enhancing the verification environment. The ideal candidate should have a Master's degree in Electronics/Electrical/Computer Engineering with 2+ years of industry experience.

Requirements

  • Familiarity with CPU architectures and superscalar designs and industry-leading RISC processors
  • Exposure to various ASIC design verification tools with good digital design concepts
  • Knowledge and experience with Interconnect protocols like AXI/ACE/OCP/CHI
  • Scripting experience in Python/Perl/TCL/Shell
  • Experience in creating functional test plans and implementing them as part of pre-silicon verification
  • Strong knowledge of Verilog/SystemVerilog/C/C++/Assembly
  • Strong analytical and problem-solving skills
  • Ability to be self-motivated with excellent communication and presentation skills
  • Ability to collaborate well with local and global teams
  • Masters's degree preferred in Electronics/Electrical/Computer Engineering with 2+ years of industry experience with a focus on functional verification in CPU verification

Responsibilities

  • Independently drive verification efforts to closure
  • Work closely with designers and architects to understand specifications at unit/top level
  • Understand use cases and develop functional test plans
  • Develop directed tests written in C, Assembly, and SystemVerilog
  • Analyze coverage and fix holes in the test plan
  • Enhance the verification environment and testbench using the latest methodologies, tools, and automation
  • Support for prototyping in FPGA and/or Emulation

Preferred Qualifications

  • Experience with RISC-V, ARM, and/or MIPS CPU
  • Experience with multi-core and coherency
  • Familiarity with functional safety flows and requirements

Benefits

  • The base salary range across the U.S. for this role is between $165,000-$195,000
  • This role may be eligible for equity, and other discretionary bonuses
  • MIPS offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package
  • The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education
  • At MIPS, youโ€™ll be a member of a fast-growing team of technologists that are creating the industryโ€™s highest performance RISC-V processors
  • Small teams that are part of a non-compartmentalized structure โ€“ youโ€™ll be able to understand and have an impact on the bigger picture
  • A great deal of autonomy, with support from some of the industryโ€™s most experienced CPU engineers
  • An unlimited growth path โ€“ with the right skills, you can decide where you want to expand and grow in your role at MIPS
  • The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers
  • MIPS provides meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!
This job is filled or no longer available